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lt4254 1 4254fb the lt ? 4254 is a high voltage hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. an internal driver controls the high side n-channel mosfet gate for supply voltages ranging from 10.8v to 36v. the part features an open-circuit detect (open) output that indicates abnormally low load current conditions. the lt4254 features an adjustable analog foldback cur- rent limit. if the supply remains in current limit for more than a programmable time, the n-channel mosfet shuts off, the pwrgd output goes low and the lt4254 either automatically restarts after a time-out delay or latches off until the uv pin is cycled low. the retry pin sets whether the part will automatically restart after an overcurrent fault or if it will latch off until the uv pin is cycled low. the pwrgd output indicates when the output voltage rises above a programmed level. an external resistor string from v cc provides programmable undervoltage and overvoltage protection. hot board insertion electronic circuit breaker/power bussing industrial high side switch/circuit breaker 24v industrial/alarm systems 12v and 24v distributed power systems allows safe board insertion and removal from a live backplane controls supply voltage from 10.8v to 36v foldback current limiting open circuit and overcurrent fault detect drives an external n-channel mosfet automatic retry or latched off operation after overcurrent fault programmable supply voltage power-up rate undervoltage and overvoltage protection open mosfet detection available in 16-lead ssop package positive high voltage hot swap controller with open-circuit detect 4254 ta01 r5 0.025 ? lt4254 sense v cc gate fb pwrgd retry uv ov timer gnd v in 24v gnd (short pin) q1 irf530 d1 cmpz5241b 11v r3 40.2k r2 40.2k r1 324k r7 100 ? r9 40.2k r6 10 ? r8 140k pwrgd v out 24v 1.5a r4 27k c l c2 33nf c3 0.1 f c1 10nf open uv = 20v ov = 40v pwrgd = 18v 24v, 2a hot swap controller v in 20v/div v out 20v/div inrush current 500ma/div pwrgd 20v/div 2.5ms/div 4245 ta02 lt4254 start-up behavior descriptio u features applicatio s u , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. c l = 168 f contact bounce typical applicatio u
lt4254 2 4254fb supply voltage (v cc ) .................................. C 0.3 to 44v sense, pwrgd ......................................... C 0.3 to 44v gate .......................................................... C 0.3 to 50v fb, uv, open ............................................. C 0.3 to 44v ov .............................................................. C 0.3 to 18v retry ........................................................ C 0.3 to 15v timer ..................................................... C 0.3v to 4.3v maximum input current (timer) ....................... 100 a operating temperature lt4254c ................................................. 0 c to 70 c lt4254i ............................................. C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 24v unless otherwise noted. symbol parameter conditions min typ max units v cc operating voltage 10.8 36 v i cc operating current 1.9 3 ma uvlh undervoltage threshold v cc low-to-high transition 3.96 4 4.04 v v uvhys hysteresis 0.25 0.4 0.55 v i inuv uv input current uv = 4.5v C0.1 C1 a uv = 0v C1.5 C3 a v ovhl overvoltage threshold v cc low-to-high transition 3.96 4 4.04 v v ovhys hysteresis 0.25 0.4 0.55 v i inov ov input current 0v ov < 6.5v 0.1 1 a v open open-circuit voltage threshold (v cc C v sense ) 2 3.5 5 mv v olopen open output low voltage i o = 2ma 0.20 0.5 v i o = 5ma 0.75 1.3 v i inopen leakage current v open = 5v 0.1 1 a v sensetrip sense pin trip voltage (v cc C v sense ) fb = 0v 5.5 12 25 mv fb 2v 40 50 60 mv i insns sense pin input current 40 70 a i pu gate pull-up current charge pump on, ? v gate = 7v C15 C35 C63 a i pd gate pull-down current any fault, v gate = 3v 40 60 80 ma ? v gate external n-channel gate drive (note 2) v gate C v cc , 12v v cc 20v 4.5 8.8 12.5 v 20v v cc 36v 10 11 12.5 v v fb fb voltage threshold fb high-to-low transition 3.96 4 4.04 v fb low-to-high transition 4.20 4.45 4.65 v v fbhys fb hysteresis voltage 0.3 0.45 0.60 v v olpgd pwrgd output low voltage i o = 1.6ma 0.25 0.4 v i o = 5ma 0.63 1.0 v order part number gn part marking 4254 4254i lt4254cgn lt4254ign consult ltc marketing for parts specified with wider operating temperature ranges. note: nc = no connect order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ gn package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 uv ov nc open pwrgd nc retry gnd v cc sense nc gate nc nc fb timer t jmax = 125 c, ja = 130 c/w
lt4254 3 4254fb t a = 25 c v cc (v) 10 1.0 i cc (ma) 1.5 2.0 2.5 3.0 15 20 25 30 4254 g03 35 40 i pwrgd pwrgd pin leakage current v pwrgd = 36v 0.1 10 a i infb fb input current fb = 4.5v C1 C0.1 a i timerpu timer pull-up current C 60 C 120 C180 a i timerpd timer pull-down current 135 a v thtimer timer shut-down threshold voltage c timer = 10nf 4.3 4.65 5 v d timer duty cycle (retry mode) 1.5 3 4.5 % v retry(th) retry threshold 0.4 0.8 1.2 v i inrtr retry input current retry = gnd C120 C85 C40 a t phluv uv low to gate low c gate = 100pf 1.7 s t plhuv uv high to gate high c gate = 100pf 6 s t phlfb fb low to pwrgd low 0.8 s t plhfb fb high to pwrgd high 3.2 s t phlsense (v cc C v sense ) high to gate low v cc C v sense = 275mv 2.5 4 s electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 24v unless otherwise noted. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: an internal clamp limits the gate pin to a maximum of 11v above v cc (under normal operating conditions). driving this pin to a voltage beyond the clamp voltage may damage the part. typical perfor a ce characteristics uw i cc vs v cc sense pin regulation voltage vs temperature, fb = 0v sense pin regulation voltage vs temperature, fb > 2v temperature ( c) C50 sense regulation voltage (mv) 13 15 17 25 75 4254 g01 11 9 C25 0 50 100 125 7 5 temperature ( c) C50 40 sense regulation voltage (mv) 45 50 55 60 C25 0 25 50 4254 g02 75 100 125
lt4254 4 4254fb typical perfor a ce characteristics uw fb pin hysteresis vs temperature gate pin pull-up current vs temperature gate pin pull-down current vs temperature ? v gate vs temperature ? v gate vs v cc i cc vs temperature fb pin threshold voltage (low- to-high) vs temperature temperature ( c) C50 C25 1.0 i cc (ma) 1.4 2.0 0 50 75 4254 g04 1.2 1.8 1.6 25 100 125 v cc = 36v v cc = 10.8v v cc = 24v temperature ( c) C50 fb threshold voltage low-to-high (v) 4.42 4.44 4.46 25 75 4254 g05 4.40 4.38 C25 0 50 100 125 4.36 4.34 temperature ( c) C50 fb threshold voltage high-to-low (v) 4.00 4.01 4.02 25 75 4254 g06 3.99 3.98 C25 0 50 100 125 3.97 3.96 fb pin threshold voltage (high- to-low) vs temperature temperature ( c) C50 300 fb hysteresis (mv) 320 360 380 400 50 480 4254 g07 340 0 C25 75 100 25 125 420 440 460 temperature ( c) C50 C45 i gate pull-up current ( a) C40 C30 C25 C20 50 0 4254 g08 C35 0 C25 75 100 25 125 C15 C10 C5 temperature ( c) C50 i gate pull-down current (ma) 75 25 4254 g09 60 50 C25 0 50 45 40 80 70 65 55 75 100 125 temperature ( c) C50 ? v gate (v gate C v cc ) (v) 11 25 4254 g10 8 6 C25 0 50 5 4 12 10 9 7 75 100 125 v cc = 18v v cc = 12v v cc = 10.8v ? v gate vs temperature temperature ( c) C50 ? v gate (v gate C v cc ) (v) 12.0 12.5 13.0 25 75 4254 g11 11.5 11.0 C25 0 50 100 125 10.5 10.0 v cc = 24v, 36v v cc = 20v v cc (v) 10 14 12 10 8 6 4 2 0 25 35 15 20 30 40 ? v gate (v gate C v cc ) (v) t a = 25 c
lt4254 5 4254fb typical perfor a ce characteristics uw timer shutdown threshold vs temperature timer pin pull-up current vs v cc uv threshold voltage (high-to- low) vs temperature timer pin pull-up current vs temperature uv hysteresis vs temperature temperature ( c) C50 C25 C150 C130 C140 timer pull-up current ( a) C110 C80 0 50 75 4254 g13 C120 C90 C100 25 100 125 timer pin pull-down current vs temperature temperature ( c) C50 timer pull-down current ( a) 3.5 25 4254 g14 2.0 1.0 C25 0 50 0.5 0 4.0 3.0 2.5 1.5 75 100 125 timer pin pull-down current vs v cc temperature ( c) C50 C25 4.0 timer shutdown threshold voltage (v) 4.4 5.0 0 50 75 4254 g16 4.2 4.8 4.6 25 100 125 temperature ( c) C50 uv threshold voltage high-to-low (v) 3.65 25 4254 g18 3.62 3.60 C25 0 50 3.59 3.58 3.66 3.64 3.63 3.61 75 100 125 uv threshold voltage (low-to- high) vs temperature temperature ( c) C50 uv threshold voltage low-to-high (v) 4.00 4.01 4.02 25 75 4254 g19 3.99 3.98 C25 0 50 100 125 3.97 3.96 temperature ( c) C50 uv hysteresis (mv) 400 450 500 25 75 4254 g20 350 300 C25 0 50 100 125 250 200 ov threshold voltage (low-to- high) vs temperature temperature ( c) C50 ov threshold voltage (low-to-high) (v) 4.00 4.01 4.02 25 75 4257 g21 3.99 3.98 C25 0 50 100 125 3.97 3.96 v cc (v) t a = 25 c 10 C126 timer pull-up current ( a) C124 C122 C120 C118 C116 15 20 25 30 4254 g17 35 40 v cc (v) 10 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 25 35 15 20 30 40 timer pull-down current ( a) t a = 25 c
lt4254 6 4254fb open output voltage vs i load open pin threshold voltage vs temperature pwrgd output voltage vs i load typical perfor a ce characteristics uw ov threshold voltage (high-to- low) vs temperature ov hysteresis vs temperature pi fu ctio s uuu v cc : input supply voltage. the positive supply input ranges from 10.8v to 36v for normal operation. i cc is typically 1.9ma. an internal circuit disables the lt4254 for inputs less than 9.8v (typ). gnd: device ground. this pin must be tied to a ground plane for best performance. fb: power good comparator input. fb monitors the output voltage through an external resistive divider. when the voltage on the fb pin is lower than the high-to-low threshold of 4v, the pwrgd pin is pulled low and released when the fb pin is pulled above the 4.45v low-to-high threshold. the fb pin also affects foldback current limit (see figure 7 and related discussion). to disable pwrgd monitoring, connect fb to the output voltage and float the pwrgd pin. timer: timing input. an external timing capacitor from timer to gnd programs the maximum time the part is allowed to remain in current limit. when the part goes into current limit, a 120 a pull-up current starts to charge the timing capacitor. when the voltage on the timer pin temperature ( c) C50 3.50 ov threshold voltage (high-to-low) (v) 3.55 3.60 3.65 3.70 C25 0 25 50 4254 g22 75 100 125 temperature ( c) C50 ov hysteresis (mv) 400 450 500 25 75 4254 g23 350 300 C25 0 50 100 125 250 200 i load (ma) 0 0 open v ol (v) 2 4 6 8 10 2 468 4254 g24 10 12 t a = 25 c temperature ( c) C50 3.0 open threshold voltage (mv) 3.5 4.0 4.5 5.0 C25 0 25 50 4254 g25 75 100 125 i load (ma) 0 0 pwrgd v ol (v) 1 2 3 4 6 2 468 4254 g26 10 12 5 t a = 25 c
lt4254 7 4254fb reaches 4.65v (typ), the gate pin is pulled low; the timer pull-up current will be turned off and the capacitor is dis- charged by a 3 a pull-down current. when the timer pin falls below 0.65v (typ), the gate pin turns on again if the retry pin is high (if the retry pin is low, the uv pin must be pulsed low to reset the internal fault latch before the gate pin will turn on). if the retry pin is grounded and the uv pin is not cycled low, the gate pin remains latched off and the timer pin will be discharged near ground. the uv pin must be cycled low after the timer pin has dis- charged below 0.65v (typ) to reset the part. if the retry pin is floating or connected to a voltage above its 1.2v threshold, the lt4254 automatically restarts after a current fault. under an output short-circuit condition, the lt4254 cycles on and off with a 3% on-time duty cycle. retry: current fault retry. retry commands the opera- tional mode of the current limit. if the retry pin is floating, the lt4254 automatically restarts after a current fault. if it is connected to a voltage below 0.4v, the part latches off after a current fault (which requires that the uv pin be cycled low in order to start normal operation again). gate: high side gate drive for the external n-channel mosfet. an internal charge pump guarantees at least 10v of gate drive for v cc supply voltages above 20v and 4.5v gate drive for v cc supply voltages between 10.8v and 20v. the rising slope of the voltage on gate is set by an external capacitor connected from the gate pin to gnd and an internal 35 a pull-up current source from the charge pump output. if the current limit is reached, the gate pin voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. if the timer pin voltage ever exceeds 4.65v, the gate pin is pulled low. the gate pin is also pulled to gnd whenever the uv pin is pulled low, or the v cc supply voltage drops below the externally programmed undervoltage threshold or above the overvoltage threshold. the gate pin is clamped internally to a maximum voltage of 11v (typ) above v cc under normal operating conditions. pi fu ctio s uuu driving this pin beyond the clamp voltage may damage the part. a zener diode is needed between the gate and source of the external mosfet to protect its gate oxide under in- stantaneous short-circuit conditions. see applications information. sense: current limit sense. a sense resistor is placed in the supply path between v cc and sense. the current limit circuit regulates the voltage across the sense resistor (v cc C sense) to 50mv while in current limit when fb is 2v or higher. if fb drops below 2v, the regulated voltage across the sense resistor decreases linearly and stops at 15mv when fb is 0v. the open output also uses sense to detect when the output current is less than (3.5mv)/r5. to defeat current limit, connect sense to v cc . pwrgd: open collector output to gnd. pwrgd is pulled low whenever the voltage on fb falls below the high-to-low threshold voltage. it goes into a high impedance state when the voltage on fb exceeds the low-to-high threshold voltage. an external pull-up resistor can pull pwrgd to a voltage higher or lower than v cc . to disable pwrgd, float this pin and connect fb to the output voltage. uv: undervoltage sense. uv is an input that enables the output voltage. when the uv pin is driven above 4v, the gate pin starts charging and the output turns on. when the uv pin goes below 3.6v, the gate pin discharges and the output shuts off. pulsing the uv pin to ground after a current limit fault cycle (timer pin dischaged to below 0.65v typ) resets the fault latch (when retry pin is low, commanding latch off operation) and allows the part to turn back on. to disable uv sensing, connect the pin to v cc through a 10k resistor. ov: overvoltage sense. ov is an input that disables the output voltage. if ov ever goes above 4v, the gate pin is discharged and the output shuts off. when ov goes below 3.6v, the gate pin starts charging and the output turns back on. to disable ov sensing, connect pin to ground. open: open circuit detect output. this pin is an open collector output that releases and is pulled high through an external resistor if the load current is less than (3.5mv/r5). if not used, leave this pin disconnected.
lt4254 8 4254fb block diagra w + C C + C + 123 a v p v p 3.5mv logic 2v 12mv ~ 50mv 9.8v 4v 4v v cc gnd 0.65v 4.65v C + C + 4v 4v pwrgd timer 4254 bd v cc sense v p gen fb ov 3 a uv retry gate open + C + C + C charge pump and gate driver + C ref gen 16 10 7 1 2 15 4 13 5 9 8 current limit internal uv timer low timer high foldback ov uv open- circuit detect
lt4254 9 4254fb test circuit ti i g diagra s w u w uv 4254 f02 gate v out +2v t plhuv 4v v out +2v t phluv 3.6v fb 4254 f03 pwrgd 1v t plhfb 4.45v 1v t phlfb 4v v cc C sense 4254 f04 gate v cc t phlsense 50mv figure 2. uv to gate timing figure 3. v out to pwrgd timing figure 4. sense to gate timing figure 1 v cc sense gate timer retry pwrgd open fb ov uv 24v gnd 3v 3v 4254 tc 100pf + C + C + C applicatio s i for atio wu u u hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. the transient currents can permanently damage the con- nector pins and glitch the system supply, causing other boards in the system to reset. the lt4254 is designed to turn on a boards supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. power-up sequence an external n-channel mosfet pass transistor (q1) is placed in the power path to control the power up of the supply voltage (figure 5). resistor r5 provides current detection and capacitor c1 controls the gate slew rate.
lt4254 10 4254fb applicatio s i for atio wu u u resistor r7 compensates the current control loop while r6 prevents high frequency oscillations in q1. when the power pins first make contact, transistor q1 is held off. if the voltage on the v cc pin is between the externally programmed undervoltage and overvoltage thresholds, and the voltage on the timer pin is less than 4.65v (typ), transistor q1 will be turned on (figure 6). the voltage at the gate pin rises with a slope equal to 35 a/ c1 and the supply inrush current is set at: i inrush = c l ? 35 a/c1 if the voltage across the current sense resistor r5 reaches v sensetrip , the inrush current will be limited by the internal current limit circuitry. the voltage on the gate pin is adjusted to maintain a constant voltage across the sense resistor and the timer pin begins to charge. when the fb pin voltage goes above the low-to-high v fb threshold, the pwrgd pin goes high. short-circuit protection the lt4254 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. the current limit is set by placing a sense resistor (r5) between v cc and sense. to limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds figure 5. 2a, 24v application 4254 f05 r5 0.025 ? lt4254 sense 13 10 5 7 8 16 15 1 2 4 9 v cc gate fb pwrgd retry uv ov timer gnd v in 24v gnd (short pin) q1 irf530 d1 cmpz5241b 11v r3 40.2k r2 40.2k r1 324k r7 100 ? r9 40.2k r6 10 ? r8 140k pwrgd v out 24v 1.5a r4 27k c l c2 33nf c3 0.1 f c1 10nf open uv = 20v ov = 40v pwrgd = 18v back as a function of the output voltage, which is sensed internally on the fb pin. when the voltage at the fb pin is 0v, the current limit circuit drives the gate pin to force a constant 12mv drop across the sense resistor. as the output at the fb pin increases, the voltage across the sense resistor increases until the fb pin reaches 2v, at which point the voltage across the sense resistor is held constant at 50mv (see figure 7). the current limit threshold is calculated as: i limit = 50mv/r5 where r5 is the sense resistor. for a 0.025 ? sense resistor, the current limit is set at 2000ma and folds back to 600ma when the output is shorted to ground. thus, mosfet dissipation under short- circuit conditions is reduced from 36w to12w. see the figure 6. start-up waveforms 2.5ms/div 4254 f06 i out 500ma/div pwrgd 20v/div v out 20v/div gate 20v/div c l = 185 f
lt4254 11 4254fb layout considerations section for important information about board layout to minimize current limit threshold error. the lt4254 also features a variable overcurrent response time. the time required for the part to regulate the gate pin voltage is a function of the voltage across the sense resistor connected between the v cc pin and the sense pin. this helps to eliminate sensitivity to current spikes and tran- sients that might otherwise unnecessarily trigger a current limit response and increase mosfet dissipation. figure 8 shows the response time as a function of the overdrive at the sense pin. timer the timer pin provides a method for programming the maximum time the part is allowed to operate in current limit. when the current limit circuitry is not active, the timer pin is pulled to gnd by a 3 a current source. when the current limit circuitry becomes active, a 123 a pull-up current source is added to the timer pin and the voltage will rise with a slope equal to 120 a/c timer as long as the circuitry stays active. once the desired maximum current limit time is known, the capacitor value is: c(nf) = 25.8 ? t(ms) whenever the timer pin reaches 4.65v (typ), the internal fault latch is set causing the gate to be pulled low and the timer pin to be discharged to gnd by the 3 a current source. the part is not allowed to turn on again until the voltage at the timer pin falls below 0.65v (typ). the timer pin must never be pulled high by a low impedance because whenever the timer pin voltage rises above the upper threshold (typically 4.65v) the pin char- acteristics change from a high impedance current source to a low impedance. if the pin must be pulled high by a logic signal, then a resistor must be put in series with the timer pin to limit the current to approximately 100 microam- peres. the resistance should be chosen as follows: r series = (v logic C 4.65v)/100 a whenever the gate pin is commanded off by any fault condition, it is discharged with a high current, turning off the external mosfet. the waveform in figure 9 shows how the output latches off following a short-circuit. the drop across the sense resistor is held at 12mv as the timer ramps up. since the output did not rise bringing fb above 2v and the current is still 12mv/r5, the circuit latches off. automatic restart if the retry pin is floating, then the functionality is as described in the previous section. when the voltage at the timer pin ramps back down to 0.65v (typ), the lt4254 turns on again. if the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. the duty cycle under short-circuit con- ditions is 3% which prevents q1 from overheating. latch off operation if the retry pin is grounded, the lt4254 will latch off after a current fault. after the part latches off, it may be applicatio s i for atio wu u u 12mv 0v 2v fb 4254 f07 50mv v cc C v sense 50 100 150 200 4254 f08 12 10 8 6 4 2 response time ( s) v cc C v sense (mv) 0 figure 7. current limit sense voltage vs feedback pin voltage figure 8. response time to overcurrent
lt4254 12 4254fb commanded to start back up. this can be commanded by cycling the uv pin to ground and then back high (this command can only be accepted after the timer pin discharges below the 0.65v typ threshold, so as to prevent overheating transistor q1). therefore, using the retry pin only, the lt4254 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. undervoltage and overvoltage detection the lt4254 uses the uv and ov pins to monitor the v cc voltage and allow the user the greatest flexibility for setting the operational thresholds. the uv and ov pins are internally connected to an analog window comparator. any time that the uv pin goes below 3.6v or the ov pin goes above 4v, the gate will be pulled low until the uv/ov pin voltages return to the normal operation voltage win- dow (4v and 3.65v, respectively). power good detection the lt4254 includes a comparator for monitoring the output voltage. the output voltage is sensed through the fb pin via an external resistor string. the comparators output (pwrgd pin) is an open collector capable of operating from a pull-up as high as 36v. the pwrgd pin can be used to directly enable/disable a power module with an active high enable input. figure 11 shows how to use the pwrgd pin to control an active low enable input power module. signal inversion is accom- plished by transistor q2 and r10. open fet detection the lt4254 can be used to detect the presence of an open fet. when the voltage across the sense resistor is less than 3.5mv, the open collector pull-down device is shut off allowing the open pin to be externally pulled high. an open fet condition is signalled when the open pin is high and the pwrgd pin is low (after the part has completed its start-up cycle). this open fet condition can be falsely signalled during start-up if the load is not activated until after pwrgd goes high. to avoid this false indication, the open and pwrgd pins should not be polled for a period of time, t startup , given by: 31 35 ?? vc a t cc startup = this can be accomplished either by a microcontroller (if available) or by placing an rc filter as shown in figure 12. once the open voltage exceeds the monitoring logic thresh- old, v thresh , and pwrgd is low, an open fet condition is signalled. in order to prevent a false indication, the rc product should be set with the following equation: rc vc a v vv cc logic logic thresh > ? ? ? ? ? ? ? ? ? ? ? ? 31 35 ?? ln C another condition that can cause a false indication is if the lt4254 goes into current limit during start-up. this will cause t startup to be longer than calculated. also, if the applicatio s i for atio wu u u figure 9. latch off waveforms figure 10. retry waveforms i out 500ma/div 2.5ms/div 4254 f09 v out 20v/div timer 5v/div gate 20v/div latch off operation i out 500ma/div 2.5ms/div 4254 f10 v out 20v/div timer 5v/div gate 1v/div automatic restart operation (short-ciruit output)
lt4254 13 4254fb lt4254 stays in current limit long enough for the timer pin to fully charge up to its threshold, the lt4254 will either latch off (retry = 0) or go into the current limit hiccup mode (retry = floating). in either case, an open fet condition will be falsely signalled. if the lt4254 does go into current limit during start-up, c1 can be increased (see power-up sequence). supply transient protection the lt4254 is 100% tested and guaranteed to be safe from damage with supply voltages up to 44v. however, voltage transients above 44v may damage the part. during a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 44v. to minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a 0.1 f bypass capaci- tor should be placed between v cc and gnd. a surge applicatio s i for atio wu u u suppressor (transorb) at the input can also prevent damage from voltage transients. gate pin a curve of gate drive vs v cc is shown in figure 13. the gate pin is clamped to a maximum voltage of 12v above the v cc voltage. this clamp is designed to withstand the internal charge pump current. an external zener diode should be used if the possibility exists for an instanta- neous low resistance short on v out to occur. at a mini- mum input supply voltage of 12v, the minimum gate drive voltage is 4.5v. when the input supply voltage is higher than 20v, the gate drive voltage is at least 10v and a figure 11. active low enable pwrgd application 4254 f11 r5 100m ? lt4254 sense 13 10 5 7 8 16 15 1 2 4 9 v cc gate fb pwrgd retry uv ov timer gnd v cc (short pin) q1 irf530 d1 cmpz5241b 11v r3 40.2k r2 40.2k r1 324k r7 100 ? r6 10 ? v out v logic r4 27k r8 140k c l r10 27k c2 33nf c3 0.1 f c1 10nf open uv = 20v ov = 40v pwrgd = 18v r9 40.2k q2 pwrgd gnd figure 12. delay circuit for open fet detection 4 r c 4254 f12 open lt4254 to monitoring logic v logic internal open collector pull-down figure 13. ? v gate vs v cc v cc (v) 10 ? v gate (v) 8 9 10 4254 f13 7 6 4 20 30 40 5 12 11 ? v gate = v gate C v cc
lt4254 14 4254fb applicatio s i for atio wu u u standard threshold mosfet can be used. in applications from 12v to 15v range, a logic level mosfet must be used. in some applications it may be possible for the v out pin to ring below ground (due to the parasitic trace inductance). higher current applications, especially where the output load is physically far away from the lt4254 will be more susceptible to these transients. this is normal and the lt4254 has been designed to allow for some ringing below ground. however, if the application is such that v out can ring more than 1v below ground, damage may occur to the lt4254 and an external diode from ground (anode) to v out (cathode) will have to be added to the circuit as shown in figure 14 (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected v cc voltage). a capacitor placed from ground to v out directly at the lt4254 pins can help reduce the amount of ringing on v out but it may not be enough for some applications. during a fault condition, the lt4254 pulls down on the gate pin with a switch capable of sinking about 55ma. once the gate voltage drops below the output voltage by a diode forward voltage, the external zener will forward bias and the output will also be discharged to gnd. in addition to the gate capacitance, the output capacitance will be discharged through the lt4254. in applications that have very large output capacitors, this could cause damage to the lt4254. therefore, the maximum output capacitance that can be used with the lt4254 is 1000 f. in applications utilizing very large external n-channel mosfets, the possibility exists for the mosfet to turn on when initially inserted into a live backplane (before the lt4254 becomes active and pulls down on gate). this is due to the drain to gate capacitance forcing current into r7 and c1 when the drain voltage steps up from ground to v cc with an extremely fast rise time. to alleviate this situation, a schottky diode should be put across r7 with the cathode connected to c1 as shown in figure 16. layout considerations to achieve accurate current sensing, a kelvin connection to the current sense resistor (r5 in typical application circuit) is recommended. the minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530 ? / . small resistances can cause large errors in high current applications. noise immunity will be improved significantly by locating resistor dividers close to the pins with short v cc and gnd traces. a 0.1 f decoupling capacitor from uv to gnd is also required. figure 15 shows a layout that meets these requirements. figure 14. negative output voltage protection diode application 4254 f14 r5 0.033 ? lt4254 sense 13 10 5 7 8 16 15 1 2 4 9 v cc gate fb pwrgd retry uv ov timer gnd v cc (short pin) q1 irf530 d1 cmpz5241b 11v mra4003t3 r3 40.2k r2 40.2k r1 324k r7 100 ? r9 40.2k r6 10 ? r8 140k v out r4 27k c l 100 f c2 33nf c3 0.1 f c1 10nf open uv = 20v ov = 40v pwrgd = 18v gnd
lt4254 15 4254fb applicatio s i for atio wu u u figure 15. recommended component placement u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uv ov nc open pwrgd nc retry gnd v cc sense nc gate nc nc fb timer 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r6 q1 v out r7 r5 r sense r4 pwrgd open gnd 4254 f15 gnd r8 d1 r3 lt4254 r2 r1 v cc c2 c1 r9 v cc short pin via 2nd layer metal gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
lt4254 16 4254fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt1641-1/lt1641-2 positive 48v hot swap controller in so-8 9v to 80v operation, active current limit, autoretry/latchoff ltc4211 single hot swap controller with multifunction current control 2.5v to 16.5v, active inrush limiting, dual level cicuit br eaker ltc4251 negative 48v hot swap controller in sot-23 floating supply from C15v, active current limiting, fast circuit breaker ltc4252-1/ltc4252-2 negative 48v hot swap controller in msop floating supply from C15v, active current limiting, power good output ltc4253 negative 48v hot swap controller and supply sequencer floating supply from C15v, active current limiting, enables three dc/dc converters lt4256-1 positive 48v hot swap controller in so-8 10.8 to 80v operation, latch-off operation, improved lt1641-1 lt4256-2 positive 48v hot swap controller in so-8 10.8 to 80v operation, auto retry operation, improved lt1641-2 lt4256-3 positive 48v hot swap controller in gn-16 10.8 to 80v operation, open circuit detect, selectable latch-off or auto retry ltc4260 positive 48v hot swap controller with i 2 c monitoring onboard 8-bit adc with i 2 c interface for board monitoring ltc4261 negative 48v hot swap controller with i 2 c monitoring onboard 10-bit adc with i 2 c interface for board monitoring ? linear technology corporation 2003 lt 1205 rev b ?printed in usa figure 16. high dv/dt mosfet turn-on protection circuit typical applicatio u 4254 f16 r5 0.033 ? lt4254 sense v cc gate fb pwrgd retry uv ov timer gnd v cc (short pin) q1 irf530 d1 cmpz5241b 11v r3 40.2k r2 40.2k r1 324k r7 100 ? r9 40.2k r6 10 ? r8 140k v out in4148w r4 27k c l 100 f c2 33nf c3 0.1 f c1 10nf open uv = 20v ov = 40v pwrgd = 18v gnd

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